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Entry (0-2 ani), Middle (2-5 ani), Senior (5-10 ani), Executive (>10 ani)

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Position duties

  • Design and verification of proprietary IXIA specific networking designs
  • Implementation on Xilinx devices (STA, design optimization for timing closure)
  • Thorough and complete documentation of implemented modules
  • Collaborating on a daily basis with SW and FPGA teams around the world

 

Requirements

  • 1-5 years of experience with FPGA or ASIC design in Verilog/VHDL
  • Strong written and spoken English and communication skills

 

Desired skills:

  • Xilinx Virtex class devices
  • Scripting languages TCL/Perl/Python
  • Network packet processing, Ethernet
  • Knowledge of computer networks, routing and switching protocols is a plus

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