Nivel cariera

Entry (0-2 ani), Middle (2-5 ani), Senior (5-10 ani), Executive (>10 ani)

Adresa/ adresele jobului

Salariu aproximativ brut oferit / luna in euro

2000 €

Acest anunt este inactiv, însă puteți trimite în continuare CV-ul Dvs. la aceasta companie

Position duties

  • Design and verification of proprietary IXIA specific networking designs
  • Implementation on Xilinx devices (STA, design optimization for timing closure)
  • Thorough and complete documentation of implemented modules
  • Collaborating on a daily basis with SW and FPGA teams around the world



  • 1-5 years of experience with FPGA or ASIC design in Verilog/VHDL
  • Strong written and spoken English and communication skills


Desired skills:

  • Xilinx Virtex class devices
  • Scripting languages TCL/Perl/Python
  • Network packet processing, Ethernet
  • Knowledge of computer networks, routing and switching protocols is a plus